1. Field of the Invention
The present invention relates to a clock supply apparatus that supplies a clock signal to a circuit block.
2. Description of the Related Art
Power supply and heat designing/manufacturing of a semiconductor integrated circuit device (hereinafter, LSI) and a system on which the LSI is mounted must be coordinated with maximum power consumption of the LSI and the system. Power supply designing/manufacturing of the LSI must also be coordinated with maximum current consumption of the LSI. When power consumption or current consumption is large, a difficulty level of designing/manufacturing and a price are high. Thus, there has been proposed a technology for reducing power consumption and current consumption of the LSI.
The power consumption of the LSI that includes a logical circuit operated in synchronization with a clock signal, except for a static part based on a leakage current, is caused by a dynamic operation based on a clock synchronization operation. The dynamic power consumption can be considered based on an operation of a flip-flop that changes its state in synchronization with a clock signal.
It is the following two operations when an active edge of an input clock signal for operating the flip-flop is input that dynamically consumes power during the operation of the flip-flop. One is a latch operation for storing input data inside, and the other is a toggle operation for changing data output during the latch operation. Power consumed during the latch operation includes not only power consumed by the flip-flop itself but also power consumed by a buffer to transmit the input clock signal. Power consumed during the toggle operation includes not only power consumed by the flop-flop itself but also power consumed by the buffer to transmit an output data signal.
Under these circumstances, as a technology for reducing power consumption and current consumption of the logical circuit, there has been proposed a clock gating technology based on enabling, which stops a clock for driving the flip-flop while enabling control of the flip-flop in the circuit is inactive. This technology reduces power consumption by control not to perform any unnecessary operation logically. Each flip-flop performs a latch operation only when necessary, and none of the flip-flops always performs a latch operation according to an active edge input of the input clock signal. Thus, current consumption can be reduced as well.
As a technology for reducing power consumption during a resetting operation of the logical circuit, there has been proposed a technology for setting a clock frequency lower during the resetting operation than that during a normal operation (discussed in Japanese Patent Application Laid-Open No. 2000-66760). This technology reduces total power consumption and power consumption per unit time by decreasing the number of times of latching during a sufficiently long resetting period to a necessary minimum.
As a technology for reducing current consumption during the resetting operation of the logical circuit, there has been proposed a technology for preventing, by controlling supplying of independent clocks to a plurality of circuit blocks during the resetting operation, overlapping of resetting periods between the clock circuits (discussed in Japanese Patent Application Laid-Open No. 2004-110718). This technology reduces instantaneous current consumption per clock cycle by performing control not to simultaneously supply clocks to all the circuit blocks during the resetting period.
However, the enabling control of the flip-flop is always active logically during the resetting operation, and hence the clock cannot be stopped by the clock gating technology based on the enabling, disabling reduction of power consumption and current consumption. As a result, depending on contents of the logical circuit, power consumption and current consumption may be higher during the resetting operation than those during the normal operation. In such a case, even when the power consumption and the current consumption can be lowered during the normal operation, designing/manufacturing of a power supply and heat must be coordinated not with the power consumption and the current consumption during the normal operation but with maximum power consumption and maximum current consumption during the resetting operation.
According to the technology for setting the clock frequency lower during the resetting operation than that during the normal operation, the reduction in total number of times of latching during the resetting period results in reduction of power consumption. However, the number of flip-flops per clock, which perform latch operations, cannot be decreased. In other words, all the flip-flops still operate with respect to the input of the active clock edge, and hence instantaneous current consumption per clock cannot be reduced. As a result, depending on contents of the logical circuit, current consumption may be higher during the resetting operation than that during the normal operation. In such a case, even when the current consumption during the normal operation can be reduced by the clock gating technology based on the enabling, designing/manufacturing of a power supply must be coordinated not with the current consumption during the normal operation but with maximum current consumption during the resetting operation.
According to the technology for preventing overlapping of the resetting periods between the circuit blocks by controlling supplying of the independent clocks to the plurality of circuit blocks during the resetting operation, current consumption can be reduced by performing control to prevent overlapping of all the resetting periods of the circuit blocks. However, when there is a logical connection among the circuit blocks, no overlapping of all the resetting periods may disable complete resetting, because of the following mechanism.
A flip-flop with no reset terminal can reset clock synchronization by arranging a logical circuit so that input data can be fixed to low (L) or high (H) while a reset signal is active. Depending on a design of a logical circuit, a flip-flop where input data is fixed to neither L nor H even while the reset signal is active may be included. Such a flip-flop can be reset only when an active clock edge is input after all the flip-flops logically connected to an input data pin have been reset. Thus, when the flip-flops logically connected to the input data pin of the flip-flop include a flip-flop of another circuit block yet to be reset, this flip-flop cannot be reset. In other words, when the flip-flops included in the plurality of circuit blocks are connected to one another, independent setting of the resetting periods of all the circuit blocks may lead to incomplete resetting.